debugging time中文是什么意思

發(fā)音:

中文翻譯
造句

調(diào)試時(shí)間

debug vt. (-bugged; -bugging) 1.驅(qū)除 ...
time n. 1.時(shí)，時(shí)間，時(shí)日，歲月。 2.時(shí)候，時(shí)刻；期間； ...
just-in-time debugging 實(shí)時(shí)調(diào)試
real time debugging routine 實(shí)時(shí)調(diào)試程序
run time debugging aid 運(yùn)行時(shí)調(diào)試輔助程序
run time debugging facilities 運(yùn)行時(shí)調(diào)試功能
run time debugging language 運(yùn)行時(shí)調(diào)試語言
rda run time debugging aid 運(yùn)行期間調(diào)試助手
debugging 程序調(diào)整; 除去工藝; 堤序; 調(diào)試發(fā)現(xiàn)和去除軟件失效根源的過程。; 調(diào)試來源; 調(diào)試排除故障排除程序中錯(cuò)誤; 調(diào)諧發(fā)現(xiàn)并排除計(jì)算機(jī)故障; 故障的排除; 排除錯(cuò)誤; 消除故障
arithmetic debugging 運(yùn)算調(diào)試; 運(yùn)算排錯(cuò)
asynchronous debugging 異步調(diào)試; 異步排錯(cuò)
automatic debugging 自動(dòng)查錯(cuò); 自動(dòng)調(diào)試
automation of debugging 調(diào)試自動(dòng)化
board debugging 基板調(diào)試
breakpoint debugging 斷點(diǎn)調(diào)試
cabinet debugging 控制臺(tái)調(diào)試
connected debugging 對(duì)接聯(lián)調(diào)
console debugging 控制臺(tái)除錯(cuò); 控制臺(tái)調(diào)試
control debugging 控制臺(tái)調(diào)整
debugging activity 調(diào)試活動(dòng)
debugging aid 調(diào)試輔助程序; 調(diào)試輔助手段, 調(diào)試工具; 調(diào)試工具
debugging aids 翟輔助程序; 調(diào)試輔助程序; 調(diào)試工具
debugging by backtracking 回溯糾錯(cuò)
debugging by induction 歸納法糾錯(cuò)
debugging c c 程序調(diào)試實(shí)用手冊(cè)

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例句與用法

The trend is to write compilers in high-level languages, because of the reduced amount of programming time and debugging time .
目前傾向使用高級(jí)語言編寫編譯程序，因?yàn)檫@減少了大量的編程序和調(diào)程序的時(shí)間。
This allows a component creator to ship the visualizer in a dll to be called only at debug time
這樣一來，組件創(chuàng)建者便可以通過僅在調(diào)試時(shí)調(diào)用的dll提供可視化工具。
Ensures that all variables are declared and spelled correctly , which reduces debugging time . the
可確保所有變量的聲明方式和拼寫方式均正確無誤，這樣就縮短了調(diào)試時(shí)間。
At the same time , the signal integrity about the key circuit is simulated with the hyperlynx software . with which the circuit performation is enhanced , the debugging time and the cost are reduced
并且通過mentorgraphics公司的hyperlynx仿真軟件對(duì)電路關(guān)鍵部分的信號(hào)完整性進(jìn)行了仿真,以此提高了電路設(shè)計(jì)的成功率,縮短了產(chǎn)品設(shè)計(jì)調(diào)試周期,減少了成本損失。
The intelligentized indoors communication systems in this paper has assed the system debugging time after time , and used in slap - up dwelling house , which proves fully its rationality and feasibility , it possess the wide market foreground
本文中的智能信息家電系統(tǒng)已經(jīng)過多次系統(tǒng)調(diào)試，并在高檔住宅中使用，充分證明了其合理性和可行性，具有廣闊的市場(chǎng)前景。
Designer can synthesize the pci core and the user ' s logic into an fpga chip , and can do simulation analysis to test the pci core and the user ' s logic . this technique can increase the design and debugging time , develop the capability of the system
設(shè)計(jì)者可以將pci用戶邏輯與pcicore集成在一片fpga里，并且可以在頂層通過仿真來驗(yàn)證pci接口以及用戶邏輯設(shè)計(jì)的正確與否，這樣可以大幅度提高調(diào)試速度，縮短開發(fā)周期，提高電路板的集成度和系統(tǒng)的性能。

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